Design Verification
Training Provider: NANYANG TECHNOLOGICAL UNIVERSITY
Course Reference: TGS-2025058641
S$2,025
Original: S$4,050
Save S$2,025
About This Course
To acquire basic knowledge in verification of digital electronics. The course focuses on verifying the functionality of digital circuits via Verilog testbenches, assertions, creation of verification plans, collecting code coverage, and an introduction to the Universal Verification Methodology (UVM).
At the end of the course, learners will be able to:
1. Describe the verification methodology.
2. Define the testbench.
3. Develop the stimulus generation.
4. Determine the Correctness.
5. Perform assertion-based verification and coverage, gate-level verification, and establish the verification plan.
What You'll Learn
Step into the future with our meticulously crafted course, tailored for engineers and professionals poised to excel in the manufacturing, digital electronics, integrated circuit (IC) Design, and design automation realms. Equally relevant for diverse industries harnessing scripting languages for automation, this course ignites your potential for career growth and transformation.
With a focus on topics in verification of digital electronics, the course equips learners with basic skill sets in verifying the functionality of digital circuits via Verilog testbenches, assertions, creation of verification plans, and collection of code coverage. The Universal Verification Methodology (UVM) will also be introduced.
This course comprises 20 hours of lectures and 9 hours of enriching hands-on laboratory sessions ensure mastery at both conceptual and practical application levels. This transformative experience moulds you into a proactive and adaptive thinker, primed for the challenges and innovation-driven demands of advanced manufacturing.
With a focus on topics in verification of digital electronics, the course equips learners with basic skill sets in verifying the functionality of digital circuits via Verilog testbenches, assertions, creation of verification plans, and collection of code coverage. The Universal Verification Methodology (UVM) will also be introduced.
This course comprises 20 hours of lectures and 9 hours of enriching hands-on laboratory sessions ensure mastery at both conceptual and practical application levels. This transformative experience moulds you into a proactive and adaptive thinker, primed for the challenges and innovation-driven demands of advanced manufacturing.
Entry Requirements
There are no formal entry requirements or prior qualifications needed.
Course Details
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