Design for Test
About This Course
The module covers various topics relevant to very large-scale integration (VLSI) testing. Learners will obtain comprehensive knowledge on testability from the device level to the architecture level.
At the end of the course, learners will be able to:
1. Attain a basic understanding of VLSI testing.
2. Describe the integrated circuit (IC) device failure mechanisms and accelerated tests.
3. Define the fault models and testability concepts.
4. Develop test generation and fault simulation algorithms.
5. Conduct IDDQ (Direct Drain Quiescent Current) testing and functional testing.
6. Explain the design for testability concept and examples.
7. Carry out Built-in self-test (BIST) and the random-access memory test.
8. Explain the IEEE (Institute of Electrical and Electronics Engineers) test standards.
What You'll Learn
With a focus on topics relevant to very large-scale integration (VLSI) testing, learners will obtain comprehensive knowledge on the testability from device to architectural level.
This course comprises 20 hours of lectures and 9 hours of enriching hands-on laboratory sessions ensure mastery at both conceptual and practical application levels. This transformative experience moulds you into a proactive and adaptive thinker, primed for the challenges and innovation-driven demands of advanced manufacturing.
Entry Requirements
There are no formal entry requirements or prior qualifications needed.